1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems having a plurality of data processing units sharing common memory locations, data processing units typically referred to as being tightly coupled. The use of buffer or cache memory units associated with each data processing unit can result in the presence of a plurality of copies of a data group. Because each data processing unit has independent access to the data group, any copy of the data group can be changed by the associated data processing unit, rendering invalid the copies of the data group in other data processing units.
2. Description of the Related Art
Because of the increasing importance of tightly coupled data processing units to provide increased flexibility and computational power in data processing systems along with the almost universal use of cache memory units to enhance performance of data processing units, the problem of the coherency of the copies of the data groups has become increasingly important and several techniques for addressing the data group coherency problem have been disclosed. The general problem of coherency in cache memory units has been considered in the article "Implementing A Cache Consistency Protocol" by R. H. Katz et al (0149-7111/85/0000/0276), IEEE, 1985; "Competitive Snoopy Caching" by A. R. Karlin (Proceedings of the 27th Annual Symposium on the Foundations of Computer Science, IEEE, 1986) and "Synchronization, Coherence and Event Ordering in Multiprocessors" by M. Dubois et al (0018-9162/88/0200-0009, IEEE, 1988). In the article "Firefly: A Multiprocessor Workstation" by C. P. Thacker et al (0018-9340/88/0800-0909, IEEE, 1988), a coherency technique is described for a "write-back" cache protocol that involves a plurality of tag signals. In U.S. Pat. No. 4,228,503 invented by J. C. Waite et al, issued Oct. 14, 1980 and entitled "Multiplexed Directory for Dedicated Cache Memory System", each cache memory unit has access to all other cache units and can invalidate entries in the other cache units when the conditions are appropriate. In U.S. Pat. No. 4,322,795 invented by R. E. Lange et al, issued Mar. 30, 1982 and entitled "Cache Memory Utilizing Selective Clearing and Least Recently Used Updating", each central processing unit has associated therewith a cache memory and a duplicate directory. A system control unit controls the flow of data groups between the main memory unit and the cache memories. The system controller is coupled to each duplicate directory and, when conditions are appropriate, can invalidate data groups identified in the duplicate directory and, consequently, can invalidate entries in the associated cache memory. In U.S. Pat. No. 4,385,351 by T. Matsuura et al, issued May 24, 1983, and entitled "Multiprocessor System with Apparatus for Propagating Cache Buffer Invalidation Signals Around a Circular Loop", all the cache units are coupled in a loop, thereby permitting activity involving one cache unit to be communicated to all the other cache memory units for appropriate response. In U.S. Pat. No. 4,394,731 by F. O. Flusche et al, issued Jul. 19, 1983 and entitled "Cache Storage Line Shareability Control for a Multiprocessor System" and in U.S. Pat. No. 4,484,267 invented by R. P. Fletcher, issued Nov. 20, 1984 and entitled "Cache Sharing Control In A Multiprocessor", a system controller contains a duplicate directory of the data groups stored in cache memory units of associated processors. The system controllers are coupled (i.e., by the XI bus) and transfer status information relating to signal groups between system controllers. In addition, the disclosure involves store in cache units in which the current copy of a data group is not in the main memory, but in the associated cache unit. In addition, the operation of the invention involves novel status signals for the signal groups. In U.S. Pat. No. 4,410,944 invented by R. K. Kronies, issued Oct. 18, 1983 and entitled "Apparatus and Method for Maintaining Cache Memory Integrity in a Shared Memory Environment", each shared memory has monitoring and control capability for monitoring read and write requests and, under appropriate conditions, can invalidate the entries in the cache units. In U.S. Pat. No. 4,426,681 invented by P. C. A. Bacot et al, issued Jan. 17, 1984 and entitled "Process and Device for Managing the Conflicts Raised by Multiple Access to Same Cache Memory of a Digital Data Processing System Having Plural Processors, Each Having a Cache Memory", the conflicts described relate to conflicts resulting in simultaneous processing of a plurality of requests and not to conflicts in the coherency of a plurality of data groups in the data processing system. In U.S. Pat. No. 4,471,429 invented by M. G. Porter et al, issued Sept. 11, 1984 and entitled "Apparatus for Cache Clearing", a central processing unit having a cache unit, a system control unit, and a duplicate directory associated therewith is disclosed. Each system control unit is coupled to all the duplicate cache unit directories, all system controllers, and the main memory. All system control units receive information concerning activity involving the main memory and can, under appropriate conditions, interrogate the duplicate directory to determine when a selected signal group has been accessed When the selected signal group has been accessed, then the selected signal group in the cache unit is invalidated. In U.S. Pat. No. 4,622,631 invented by S. J. Frank, issued November 11, 1986 and entitled "Data Processing System Having a Data Coherence Solution", only one copy of a data group in a data processing system is described as the "correct" copy (i.e., designated in terms of current owner by the reference). Apparatus is provided for transferring the correct copy of the data group to a cache unit of a requesting central processing unit. In U.S. Pat. No. 4,747,043 invented by P. K. Rodman, issued on May 24, 1988 and entitled "Multiprocessor Cache Coherence System", a separate processor for identifying and storing information related to data group activity is described. The separate (cache coherence) processor provides an elaborate mechanism for enforcement of a data group coherency strategy In U.S. Pat. No. 4,755,930 invented by A. W. Wilson, Jr. et al, issued Jul. 5, 1988 and entitled "Hierarchical Cache Memory System and Method", a coherency system for a multi-level cache is described which can be used with a write-through (also referred to as the store through) or write delayed cache memory protocol However, no specific implementation is provided.
The data processing system in which the present invention is incorporated has data processing system units coupled to an asynchronous system bus along with a cache memory data group coherency protocol that is generally described as a store through cache memory strategy. The coherency apparatus and techniques described by the references generally involve a plurality of status signals, an increase in the number of conducting paths coupling the cache memory unit, an increase in apparatus or describe non-bus oriented systems in which system data group activity is more accessible.
A need has therefore been felt for apparatus and an associated method that can provide data group coherency in a bus oriented data processing system using a store through cache memory strategy which does not involve a plurality of status signal or require complex apparatus.